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CG-DL-E-31082026-275860
EXTRAORDINARY
PART I—Section 1
6660 GI/2026
(1)
MINISTRY OF ELECTRONICS AND INFORMATION TECHNOLOGY
(IPHW Division)
NOTIFICATION
New Delhi, the 31st August, 2026
Subject: Semicon 2.0 - Scheme for development of Semiconductor Design and Manufacturing Ecosystem in India
F. No. W-38/6/2025-IPHW —1. Background
1.1. The National Policy on Electronics 2019 (NPE 2019) envisions positioning India as a global hub for Electronics
System Design and Manufacturing (ESDM) by creating an enabling environment for the industry to compete
globally. A key strategy under NPE 2019 is to facilitate the establishment of semiconductor wafer fabrication
facilities and the associated ecosystem for the design and fabrication of semiconductor chips.
1.2. Electronics and Semiconductors are foundational industries and are also of strategic importance for the country.
Approvals under first Semicon India Programme have generated significant interest in the semiconductor industry
and has also led to significant demand for upstream products in semiconductor ecosystem. Building on this
momentum, the Government has decided to provide and the sustained policy support to the semiconductor sector
in India by notifying the “Semicon 2.0” – Scheme for the development of Semiconductor Design and
Manufacturing Ecosystem in India. Semicon 2.0 provides fiscal support to various verticals across the complete
value chain of the semiconductor industry, ranging from chip design, fabrication and packaging to various
segments of the semiconductor ecosystem.
2.
Objective
To build a self-reliant and globally competitive semiconductor chip design and manufacturing ecosystem that
supports economic growth across all sectors, strengthens national security by enhancing supply chain resilience
and also establishes technological leadership in critical sectors.
3.
The eligible verticals under the Scheme have been divided into 6 pillars and 10 (ten) categories.
3.1.
Pillar 1 (Design): Category 1: Design of Semiconductor IPs, Chips, System-on-Chips (SoCs), and
Modules for National Importance and Strategic Priorities
3.1.1.
Objective: To build resilient, trusted, and sovereign semiconductor technologies by focusing on designing,
development, and deployment of target segment technologies for the national strategic and critical
infrastructure.
3.1.2.
Target Segment: Semiconductor Intellectual Property (IP) cores, Chips, System-on-Chips (SoCs), and
Modules for electronic products, as may be identified from time to time based on national importance and
strategic priorities. To achieve this, building blocks will be developed, including standard IPs for various types
of Compute, Memory, RF, Power, Networking, Sensors, etc.
3.1.3.
Eligibility:
| Companies incorporated and headquartered in India, having a significant operational and manpower |
|---|
| presence within the country, and that are owned and controlled by Indian citizens, shall be eligible to |
| participate. |
| Such companies may participate either independently or in consortium mode with global companies, |
|---|
| R&D organisations, academic institutions, etc. |
3.1.4.
Other Conditions:
(i)
The implementing company shall be responsible for providing long-term upgrades, support, and
maintenance of the semiconductor solutions developed.
| The implementing company will comply with Government of India rules and directives related to |
|---|
| security, export control, foreign acquisition or control, and other strategic considerations. |
| The IP rights will be co-owned by the applicant company and CDAC. CDAC will not commercially use |
|---|
| the co-owned IP until the applicant company fails to discharge its contractual obligations. |
3.1.5.
Implementation Mechanism and Fiscal Support:
| Request for Proposal (RfP) for the development of identified target segment technologies shall be issued |
|---|
| by C-DAC, detailing aspects such as fiscal support and chip design infrastructure support, project |
| duration, submission timelines, and other relevant terms and conditions. The selection of the successful |
| bidder will be done through a competitive bidding process. |
(ii)
The applications will be evaluated by the C-DAC based on technical and financial parameters, and fiscal
support will be disbursed based on approved terms and conditions of the RfP.
3.2.
Pillar 1 (Design): Category 2: Design of Semiconductor IPs, Chips and SoCs for the Commercial Sector
3.2.1.
Objective: To position India as a globally competitive hub for fabless semiconductor chip design, fostering
innovation, creation of intellectual property and product ownership by way of extending fiscal and chip design
infrastructure support, as well as catalysing venture capital funding for domestic semiconductor chip design
companies.
3.2.2.
Target Segment: Design and development of semiconductor IPs, Chips and System-on-Chips (SoCs) for
electronics products targeted to be deployed in the commercial sector.
3.2.3.
Eligibility:
| Companies incorporated and headquartered in India, having a significant operational and manpower |
|---|
| presence within the country, and owned and controlled by Indian citizens or Overseas Citizens of India |
| (OCIs), shall be eligible to participate. |
| Such companies may participate either independently or in consortium mode with global companies, |
|---|
| R&D organisations, and academic institutions. |
| Other | Conditions |
|---|---|
(i)
The implementing company will comply with Government of India rules and directives related to
security, export control, foreign acquisition or control, and other strategic considerations.
(ii)
The IP rights and all associated design and development files will remain within India.
(iii)
The eligible applicant may also avail the benefits under the Research, Development, and Innovation
(RDI) Scheme.
3.2.5.
Fiscal support:
(i)
The following shall be the fiscal support and its quantum under this category:
| S. No. | Support Structure | # | Eligible applicants | Category of support and its quantum | Mode of support |
|---|---|---|---|---|---|
| 1 | Design Infrastructure Support (DIS) | (a) | Indian academic institutions and eligible startups and MSMEs | Centralized access to national EDA Tools grid | Access will be provided to the eligible organizations, as per the terms and conditions of the respective contracts with the vendor companies. |
| | | (b) | | Centralized access to Multi-project Wafer (MPW) fabrication services | |
| | | (c) | All eligible applicants as per section 3.2.3 above | IP Cores | |
| | | (d) | | Compute Sub-Systems (CSS) | |
| | | (e) | | Post-silicon validation services access | |
| 2 | Product Design Linked Incentive (P-DLI) | (a) | Eligible start-ups/ MSMEs | Seed funding (up to ₹15 crore) | Milestone-linked advance Seed funding amounting to 50% of the project cost or ₹15 crore, whichever is lower, shall be provided per application |
| | | | | Equity co-investment (beyond ₹15 crore) | Equity co-investment shall be provided to companies that have secured funding from Venture Capital (VC) and/or Private Equity (PE) investors, on terms and conditions similar to those offered by the VC/PE investors |
| | | (b) | Eligible Companies (as per section 3.2.3 above) other than start-ups/ MSMEs | Royalty financing | Royalty financing shall be provided to the companies on a co- investment basis, subject to the condition that the beneficiary company shall pay a royalty of 5% of net revenue of the product/ technology until an amount equivalent to 1.5 times the financial support extended has been recovered |
| | | | | Equity co-investment | Equity co-investment shall be provided to the companies that have secured funding from Venture Capital (VC) and/or Private Equity (PE) investors, on terms and conditions similar to those offered by the VC/PE investors |
(ii)
Exit option: The beneficiary company may exit from any of the funding mechanisms, either on its own
discretion or upon ceasing to meet the eligibility or other conditions under the Scheme, subject to the
following:
(a) Seed funding or equity co-investment: Companies that have availed seed funding and/or equity
co-investment support may exit by paying an amount equivalent to the aggregate of the seed
funding provided and the prevailing market value of the equity held by the Government, or 1.5
times the total financial support provided (including seed funding and equity co-investment),
whichever is higher.
(b) Royalty Financing: Companies opting for royalty financing may exit by repaying 1.5 times the
financial support provided if the exit occurs within four (4) years from the date of the last
disbursement, or two (2) times the financial support provided if the exit occurs beyond four (4)
years from the date of the last disbursement.
3.3.
Pillar 1 (Design): Category 3: Deployment-Linked Incentive (DLI) for Semiconductor IPs/ Chips/ SoCs
for deployment
3.3.1.
Objective: To promote the deployment of target segment technologies by mitigating cost disabilities to
improve their competitiveness.
3.3.2.
Target Segment: Semiconductor Intellectual Property (IP) cores, Chips and System-on-chips (SoCs), which
are launched for the first time after the announcement of the scheme and have no prior sales of such products
by the applicant prior to the scheme announcement.
3.3.3.
Eligibility: Applicants eligible under Categories 1 and 2 of this scheme may submit applications under this
Category.
3.3.4.
Fiscal support: Reimbursement at the rate of 9% on net sales of target segments for a period of five (5) years,
subject to a maximum incentive ceiling of ₹30 crore per application and an aggregate ceiling of ₹120 crore per
company (including group companies) across multiple products within the target segments.
3.4.
Pillar 2 (Machines and Materials): Category 4: Semiconductor manufacturing ecosystem
3.4.1.
Objective: To build a self-reliant and globally competitive semiconductor manufacturing ecosystem and
enabling its participation in the global electronics value chains.
3.4.2.
Target Segment: Setting up R&D facilities for semiconductor equipment, manufacturing facilities for
semiconductor-grade raw materials and Manufacturing and/or Assembly of Capital Equipment/refurbish
Equipment, their sub-Assemblies, components for use in semiconductor fabrication and packaging
facilities, and Semiconductor Test and characterization Facilities.
3.4.3.
Eligibility and Fiscal Support: The applicants are expected to “Own or possess licensed technologies for
the proposed unit”, except for the Test and characterisation facility.
The eligible sub-verticals, their capital investment threshold and fiscal support from Government of India are listed as
below:
| S.N. | Eligible Sub-Verticals | Minimum Capital Investment Threshold | Minimum Revenue Threshold (including Group Companies) in any of the three FYs preceding the year of application submission | Fiscal support from Government of India |
|---|---|---|---|---|
| (a) | Setting up R&D facilities for semiconductor equipment | ₹300 crore | ₹120 crore | 30% of Capital Expenditure on pari-passu basis |
| (b) | Setting up manufacturing facilities for semiconductor grade Raw Materials (Front end/ Back-end), such as, but not limited to, Wafer, Photo mask, Photoresist, Substrate, chemicals, gases, materials, glass for display fab etc. | ₹50 crore | ₹20 crore | |
| (c) | Semiconductor Test and characterization Facilities | ₹100 crore | ₹40 crore | |
| (d) | Manufacturing and/or Assembly of Equipment/refurbish Equipment, Sub-Assemblies, Components for use in all semiconductor fabrication and packaging facilities | ₹300 crore | ₹120 crore | 30% of Capital Expenditure on pari-passu basis and Production Linked Incentive (PLI) of 10% / 8% / 6% / 4% / 2% of BoM value sourced from |
| domestic manufactures. The PLI incentive will be applicable for 5 years starting from FY 2028-29 subject to an overall ceiling of 50% of the eligible capex. |
|---|
3.5.
Pillar 3 (Setting up more Fabs): Category 5: Silicon Semiconductor Wafer Fabs
3.5.1.
Objective: To build a globally competitive semiconductor fabrication facility to make India self-reliant and
participate in the global electronics value chains.
3.5.2.
Target Segment: Setting up Silicon Semiconductor Wafer Fabs
3.5.3.
Eligibility and Fiscal Support:
| Technology | Wafer Size | Installed Capacity |
|---|---|---|
| | 300 mm | 40,000 Wafer Starts/ Month or more |
| Operational Experience | Own or possess production grade licensed technologies for proposed technology process | |
| Minimum Capital Investment Threshold | Minimum Capital Investment of ₹20,000 crore (₹200 billion) | |
| Minimum Revenue Threshold | Minimum Revenue of ₹7,500 crore (₹75 billion) (including Group Companies / Joint Venture) in any of the three financial years preceding the year of application submission | |
| Fiscal support from Government of India | Fiscal support as percentage of eligible capital expenditure | |
| | 40% on Pari-passu basis | |
3.6.
Pillar 3 (Setting up more Fabs): Category 6: Compound Semiconductors / Photonics / Sensors (including
MEMS) Fab / Discrete Semiconductors Fab
3.6.1.
Objective: To build a globally competitive semiconductor manufacturing facility across different technologies
to make India self-reliant and participate in the global electronics value chains.
3.6.2.
Target Segment: Setting up Compound Semiconductors / Photonics / Sensors (including MEMS) Fab /
Discrete Semiconductors Fab.
3.6.3.
Eligibility and Fiscal Support:
| Wafer Size | 200 mm or more | Sensor (Including MEMS) Fabs |
|---|---|---|
| | 150mm or more | Compound Semiconductors and Discrete Fab |
| | 100 mm or more | Fabs for photonics applications |
| Capacity | 500 Wafer Starts / Month or more | |
| Operational Experience | Own or possess production grade licensed technologies for the proposed technology process | |
| Minimum Capital Investment Threshold | Minimum Capital Investment of ₹500 crore (₹5 billion) | |
| Minimum Revenue Threshold | Minimum Revenue of ₹200 crore (₹2 billion) (including Group Companies / Joint Venture) in any of the three financial years preceding the year of application submission | |
| Fiscal support from Government of India | Fiscal support as percentage of eligible capital expenditure | |
| | 35% on Pari-passu basis | |
3.7.
Pillar 3 (Setting up more Fabs): Category 7: Display Fabs:
3.7.1.
Objective: Build a self-reliant and globally competitive display ecosystem of the target segment and thereby
participate in the global electronics value chains.
3.7.2.
Target Segment: Setting up of Display Fabs based on technologies including OLED, Micro LED, and LCD.
3.7.3.
Eligibility and Fiscal Support:
| Technology | OLED (Generation 6 or above) |
|---|---|
| Capacity | 30,000 Panels / month or more |
| Operational Experience | Own or possess production grade licensed technologies for proposed |
| | technology process |
| Minimum Capital Investment | |
| | Minimum Capital Investment of ₹10,000 crore |
| Threshold | |
| | Minimum Revenue of ₹5,000 crore (₹50 billion) (including Group Companies |
| Minimum Revenue Threshold | Joint Venture) in any of the three financial years preceding the year of application |
| | submission |
| Fiscal support from | Fiscal support as percentage of eligible capital expenditure |
| Government of India | 35% on Pari-passu basis |
| Technology | Micro LED Technology |
|---|---|
| Capacity | Panel area of 500 sqm/month or more |
| Operational Experience | Own or possess production grade licensed technologies for proposed |
| | technology process |
| Minimum Capital Investment | |
| | Minimum Capital Investment of ₹ 1,500 crore |
| Threshold | |
| | Minimum Revenue of ₹600 crore (₹6 billion) (including Group Companies |
| Minimum Revenue Threshold | Joint Venture) in any of the three financial years preceding the year of application |
| | submission |
| Fiscal support from | Fiscal support as percentage of eligible capital expenditure |
| Government of India | 35% on Pari-passu basis |
| Technology | LCD (Generation 8 or above) |
|---|---|
| Capacity | 60,000 Panels / month or more |
| Operational Experience | Own or possess production grade licensed technologies for proposed |
| | technology process |
| Minimum Capital Investment | |
| | Minimum Capital Investment of ₹10,000 crore |
| Threshold | |
| | Minimum Revenue of ₹5,000 crore (₹50 billion) (including Group Companies |
| Minimum Revenue Threshold | Joint Venture) in any of the three financial years preceding the year of application |
| | submission |
| Fiscal support from | Fiscal support as percentage of eligible capital expenditure |
| Government of India | 35% on Pari-passu basis |
3.8.
Pillar 4 (Further strengthening the ATMP/OSAT industry): Category 8: Semiconductor Assembly,
Testing, Marking and Packaging (ATMP) / Outsourced Semiconductor Assembly and Test (OSAT)
Facility:
3.8.1.
Objective: Build a self-reliant and globally competitive semiconductor ATMP/OSAT facility.
3.8.2.
Target Segment: Setting up Semiconductor Assembly, Testing, Marking and Packaging (ATMP) / Outsourced
Semiconductor Assembly and Test (OSAT) Facility.
3.8.3.
Eligibility and Fiscal Support:
| Category | Advanced Packaging (2.5D/3D packaging, Wafer-Level chip scale Packaging, Heterogenous integration) and Advanced Substrate |
|---|---|
| Operational Experience | Own or possess production grade licensed technologies for the proposed technology process |
| Minimum Capital Investment Threshold | Minimum Capital Investment of ₹1000 crore |
| Minimum Revenue Threshold | Minimum Revenue of ₹200 crore (including Group Companies / Joint Venture) in any of the three financial years preceding the year of application submission |
| | Fiscal support as percentage of eligible capital expenditure |
| Fiscal support from Government of India | 35% on Pari-passu basis |
|---|---|
| Category | Legacy Packaging |
|---|---|
| Operational Experience | Own or possess production grade licensed technologies for the proposed technology process |
| Minimum Capital Investment Threshold | Minimum Capital Investment of ₹1000 crore |
| Minimum Revenue Threshold | Minimum Revenue of ₹200 crore (₹2 billion) (including Group Companies / Joint Venture) in any of the three financial years preceding the year of application submission |
| Fiscal support from Government of India | Fiscal support as percentage of eligible capital expenditure |
| | 25% on Pari-passu basis |
3.9.1.
Objective: Strengthen the R&D capability in semiconductor and display manufacturing technologies in the
country.
3.9.2.
Target Segment: Develop technologies, including advanced process technologies for CMOS-based
fabrication, Silicon Photonics, display fabrication, chiplet-based technologies for advanced packaging or any
other advanced technologies related to semiconductors.
3.9.3.
Eligibility: Semiconductor companies, either on their own or in a consortium with academic institutions or
R&D organisations, etc.
3.9.4.
Fiscal Support: Up to 75% (including State Incentive) of the Project Cost (Capex and Opex), which will
include eligible capital expenditure and operational expenditure. This may also include the part funding under
the Research, Development, and Innovation (RDI) Scheme, wherever necessary. Proposals will be considered
for the fiscal support by the Nodal Agency.
3.9.5.
Separate guidelines containing details regarding eligibility criteria, fiscal support, etc. shall be released with
the approval of Minister for Electronics and Information Technology.
3.10.
Pillar 6 (Talent Development): Category 10: Talent Development
3.10.1.
Objective: Develop a robust, multi-tiered semiconductor talent ecosystem in India by nurturing skilled
professionals across design, fabrication and packaging domains and related ecosystem, spanning
undergraduate, postgraduate, doctoral, and shop-floor level technician/operators, thereby enabling self-
reliance, global competitiveness, and sustained innovation in the semiconductor industry.
3.10.2.
Target Segment:
(i)
Design: To provide access of advance chip design tools, multi-project wafer (MPW) fabrication services,
post-silicon validation tools etc. including capacity building projects.
(ii)
Manufacturing: Establish and support dedicated training infrastructure and leverage and support existing
infrastructure for hands-on training of shop-floor manpower, and strengthen existing national nanofabrication
and process laboratories to impart practical, industry-relevant training.
3.10.3.
Eligibility: Indian academic institutions, R&D organizations and laboratories, scientific societies, Domestic
Training institutions/Organizations.
3.10.4.
Fiscal Support: Up to 75% (including State Incentive) of the Project Cost (Capex and Opex), which will
include eligible capital expenditure and operational expenditure. Proposals will be considered for the fiscal
support by the Nodal Agency.
3.10.5.
Separate guidelines containing details regarding eligibility criteria, percentage of fiscal support etc. shall be
released with the approval of Minister for Electronics and Information Technology.
4.
Project duration: The duration of the projects to be supported under this scheme, shall be determined on project-
to-project basis preferably upto 6 years.
5. Application Procedure: The scheme shall be initially open for applications for a period of Three (3) years. The
applications are to be submitted through portal of the Nodal Agency during the application window.
6. Nodal Agency
6.1.
India Semiconductor Mission (ISM) shall be the Nodal Agency for Semicon 2.0. The Nodal agency may
implement the three categories related to design and deployment of IPs/Chips/SoCs with the help of CDAC.
6.2.
ISM will be responsible for inviting the applications, carrying out technical and financial appraisal of the
applications received under the scheme; recommending selection of applicants; and carrying out other
responsibilities as assigned by the Ministry of Electronics and Information Technology from time to time.
6.3.
To promote niche developments and the culture of innovation, ISM may announce semiconductor deep tech
awards from 2026.
7. Approval of Applicant(s)
7.1.
Evaluation by Nodal Agency: The applicant(s) will be evaluated by the Nodal Agency on an ongoing basis.
Evaluation will include financial and technical parameters such as process technologies, project implementation
capacity, operation capability, offtake etc.
7.2.
Upon appraisal/ evaluation, the applications shall be forwarded by the Nodal Agency to Ministry of Electronics
and Information Technology.
7.3.
The proposal(s) as recommended by the Nodal Agency for semiconductor design categories and Talent
development with the project cost less than ₹100 crore will be approved by Secretary, MeitY. Projects costing
above ₹100 crore and up to ₹500 crore will be approved by Minister of Electronics and Information Technology.
For project cost more than ₹500 crore, the proposal(s) as recommended by the Nodal Agency be placed by
Ministry of Electronics and Information Technology for approval by Cabinet.
7.4.
For all other categories, the proposal(s) as recommended by the Nodal Agency should be placed by Ministry of
Electronics and Information Technology for approval by Cabinet. After the approval is accorded by the Union
Cabinet, these will be forwarded by Ministry of Electronics and Information Technology to the Nodal Agency
for communication to the applicant(s).
8. Disbursement of Incentives: Ministry of Electronics and Information Technology shall make budgetary provisions
for disbursal of fiscal support to approved applicant(s) under the schemes. The disbursement of the fiscal support
shall be done by the Nodal Agency based on approval conditions.
9. Impact Assessment: Mid-term appraisal of the schemes shall be done after three years of their implementation or
as per requirement to assess the impact of the schemes. Based on such an impact assessment, a decision may be
taken to continue/modify the scheme.
10. Scheme Guidelines: The scheme guidelines shall be issued by Ministry of Electronics and Information Technology
(MeitY) separately.
11. Amendment of Scheme and Guidelines: The scheme and its guidelines may be reviewed and amended
periodically or as per requirement with the approval of Minister of Electronics and Information Technology.
SUSHIL PAL, Jt. Secy.
and Published by the Controller of Publications, Delhi-110054.
VINOD
KUMAR
Digitally signed
by VINOD KUMAR
Date: 2026.08.31
11:07:29 +05'30'
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